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october 2011 doc id 15108 rev 2 1/41 1 m41t66 serial real-time clock with alarms features counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century 32 khz crystal oscilla tor integrating load capacitance and high crystal series resistance operation oscillator stop detect ion monitors clock operation serial interface supports i 2 c bus (400 khz) 525 na timekeeping current at 3 v low operating current of 35 a (at 400 khz) timekeeping down to 1.0 v 1.3 v to 4.4 v i 2 c bus operating voltage ? allows use in lithium ion rechargeable applications 32 khz square wave on power-up to drive a microcontroller in low-power mode programmable (1 hz to 32 khz) square wave programmable alarm with interrupt function accurate programmable watchdog (from 62.5 ms to 31 min) software clock calibration to compensate deviation of crystal due to temperature automatic leap year compensation operating temperature of ?40 to 85 c lead-free 16-pin qfn package qfn16 3 mm x 3 mm www.st.com
contents m41t66 2/34 doc id 15108 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.1 bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.2 start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.4 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.5 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9 initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
m41t66 list of tables doc id 15108 rev 2 3/34 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. m41t66 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. initial power-on default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 14. qfn16 ? 16-lead, quad, flat package, no lead, 3 x 3 mm body size, mech. data . . . . . . . 29 table 15. carrier tape dimensions for qfn16 (3 mm x 3 mm) package . . . . . . . . . . . . . . . . . . . . . . 30 table 16. reel dimensions for 12 mm carrier tape - qfn16 package . . . . . . . . . . . . . . . . . . . . . . . . 31 table 17. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
list of figures m41t66 4/34 doc id 15108 rev 2 list of figures figure 1. m41t66 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. m41t66 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. m41t66 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. hardware hookup for supercap? backup operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 12. calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 14. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 16. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 17. qfn16 ? 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline . . . . . . . . . . . 28 figure 18. qfn16 ? 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended footprint . . . . . . 29 figure 19. 32 khz crystal + qfn16 vs. vsoj20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 20. carrier tape for qfn16 (3 mm x 3 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 21. reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
m41t66 description doc id 15108 rev 2 5/34 1 description the m41t66 is a low-power serial real-time clock (rtc) with a built-in 32.768 khz oscillator (external crystal controlled). eight registers are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. an additional 8 registers provide status/control of alarm, square wave, calibration, and watchdog functions. addresses and data are transferred serially via a two line, bidirectional i 2 c interface. the built-in address register is incremented automatically after each write or read data byte. functions available to the user include a time-of-day clock/calendar, alarm interrupts, programmable square wave output, and watchdog output. the eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24-hour bcd format. corrections for 28-, 29- (leap year), 30- and 31-day months are made automatically. the m41t66 is supplied in a 16-pin qfn. figure 1. m41t66 logic diagram 1. open drain 2. defaults to 32 khz on power-up 3#, 6 ## -4 6 33 3$! )21/54 317 8) 8/ !)
description m41t66 6/34 doc id 15108 rev 2 figure 2. m41t66 connections 1. sqw output defaults to 32 khz upon power-up 2. open drain figure 3. m41t66 block diagram 1. open drain 2. defaults to 32 khz on power-up .# .# .# .# .# .# 8) 8/ 317 6 33 6 33 6 ## .# 3#, 3$! )21/54 !) table 1. signal names xi oscillator input xo oscillator output sda serial data input/output scl serial clock input irq /out interrupt or out output (open drain) sqw programmable square wave - defaults to 32 khz on power-up (open drain) v cc supply voltage v ss ground 2%!,4)-%#,/#+ #!,%.$!2 24#7!,!2- /3#),, !4/2&!), $%4%#4 315!2%7!6% 7!4#($/' )21/54 317 /&)% 3$! 3#, !&% 317% ) # ).4%2&!#% +(z /3#),, !4/ 2 84!, !)a
m41t66 description doc id 15108 rev 2 7/34 figure 4. hardware hookup for supercap? backup operation 1. open drain 2. for a crystal with a load capacitance (c l ) of 12.5 pf, two parallel ex ternal 12.5 pf capacitors (c 1 and c 2 ) must be added to achieve better clock accuracy. 3. it can also be connecte d to another power supply. 4. due to the output buffer circuitry used for the sqw output, this pin must not be taken to a voltage greater than v cc . diode required on sqw pin for supercap? (or battery) backup. low threshold bat42 diode recommended. !)b 6 ## 0ort 317). 3erial#lock,ine 3e rial$ata,ine 8/ 8) -4 -#5 6 33 )21/54 317 3$! 3#, 6 ## 6 ## # #
operation m41t66 8/34 doc id 15108 rev 2 2 operation the m41t66 clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave address (d0h). the 16 bytes contained in the device can then be accessed sequentially in the following order: 1 st byte: tenths/hundredths of a second register 2 nd byte: seconds register 3 rd byte: minutes register 4 th byte: hours register 5 th byte: square wave/day register 6 th byte: date register 7 th byte: century/month register 8 th byte: year register 9 th byte: calibration register 10 th byte: watchdog register 11 th - 15 th bytes: alarm registers 16 th byte: flags register 2.1 2-wire bus characteristics the bus is intended for communication between different ics. it consists of two lines: a bidirectional data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line, while the clock lin e is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined: 2.1.1 bus not busy both data and clock lines remain high. 2.1.2 start data transfer a change in the state of the data line, from high to low, while the clock is high, defines the start condition. 2.1.3 stop data transfer a change in the state of the data line, from low to high, while the clock is high, defines the stop condition.
m41t66 operation doc id 15108 rev 2 9/34 2.1.4 data valid the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start co ndition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition a device that gives out a message is called ?transmitter,? the receiving device that gets the message is called ?receiver.? th e device that controls the message is called ?master.? the devices that are controlled by the master are called ?slaves.? 2.1.5 acknowledge each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition. figure 5. serial bus data transfer sequence !) $!4! #,/#+ $!4!,).% 34!",% $!4!6!,)$ 34!24 #/.$)4)/. #(!.'%/& $!4!!,,/7%$ 34/0 #/.$)4)/.
operation m41t66 10/34 doc id 15108 rev 2 figure 6. acknowledgement sequence 2.2 read mode in this mode the master reads the m41t66 slave after setting the slave address (see figure 8 on page 11 ). following the write mode control bit (r/w =0) and the acknowledge bit, the word address 'an' is written to the on-chip address pointer. next the start condition and slave address are repeated followed by the read mode control bit (r/w =1). at this point the master transmitter becomes the master receiver. the data byte which was addressed will be transmitted and the master re ceiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. the m41t66 slave transmitter will now pl ace the data byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to ?an+2.? this cycle of reading consecutive addresses will continue until the mast er receiver sends a stop condition to the slave transmitter. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume due to a stop condition or when the pointer increments to any non-clock address (08h-0fh). note: this is true both in read mode and write mode. an alternate read mode may also be implemented whereby the master reads the m41t66 slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 9 on page 11 ). !) $!4!/54054 "92%#%)6%2 $!4!/54054 "942!.3-)44%2 3#,&2/- -!34%2 34!24 #,/#+05,3%&/2 !#+./7,%$'%-%.4 -3" ,3"
m41t66 operation doc id 15108 rev 2 11/34 figure 7. slave address location figure 8. read mode sequence figure 9. alternative read mode sequence !) 27 3,!6%!$$2%33 34!24 ! -3" ,3" !) "53!#4)6)49 !#+ 3 !#+ !#+ !#+ ./!#+ 34/0 34!24 0 3$!,).% "53!#4)6)49 -!34%2 27 $!4!n $!4!n $!4!n8 7/2$ !$$2%33!n 3,!6% !$$2%33 3 34!24 27 3,!6% !$$2%33 !#+ !) "53!#4)6)49 !#+ 3 !#+ !#+ !#+ ./!#+ 34/0 34!24 0 3$!,).% "53!#4)6)49 -!34%2 27 $!4!n $!4!n $!4!n8 3,!6% !$$2%33
operation m41t66 12/34 doc id 15108 rev 2 2.3 write mode in this mode the master transmitter transmits to the m41t66 slave receiver. bus protocol is shown in figure 10 . following the start condition and slave address, a logic '0' (r/w =0) is placed on the bus and indicates to the addre ssed device that word address ?an? will follow and is to be written to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge cloc k. the m41t66 slave receiver will send an acknowledge clock to the master transm itter after it has received the slave address see figure 7 on page 11 and again after it has received the word address and each data byte. figure 10. write mode sequence !) "53!#4)6)49 !#+ 3 !#+ !#+ !#+ !#+ 34/0 34!24 0 3$!,).% "53!#4)6)49 -!34%2 27 $!4!n $!4!n $!4!n8 7/2$ !$$2%33!n 3,!6% !$$2%33
m41t66 clock operation doc id 15108 rev 2 13/34 3 clock operation the m41t66 is driven by a quartz-contro lled oscillator with a nominal frequency of 32.768 khz. the accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the rtc. the eight byte clock register (see table 2: m41t66 register map ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. a write to any clock register will result in the tenths/hundredths of seconds being reset to ?00,? and tenths/hundredths of seconds cannot be written to any value other than ?00.? bits d0 through d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month, and years. the ninth clock register is the calibration register (this is described in the clock calibration section). bit d7 of register 01h contains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. when reset to a '0' the oscillator rest arts within one second (typical). bit d7 of register 02h (minute register) contains the oscillator fail interrupt enable bit (ofie). when the user sets this bit to '1,' any conditi on which sets the oscillator fail bit (of) (see oscillator stop detection on page 21 ) will also generate an interrupt output. bits d6 and d7 of clock register 06h (century/month register) contain the century bit 0 (cb0) and century bit 1 (cb1). a write to any location within the first eight bytes of the clock register (00h-07h), including the ofie bit, rs0-rs3 bit, and cb0-cb1 bits will result in an update of the system clock and a reset of the divider chain. this could result in an inadvertent change of the current time. these non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. the eight clock registers may be read one byte at a time, or in a sequential block. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock address is being read, an update of the clock registers will be halted. this will prevent a trans ition of data during the read.
clock operation m41t66 14/34 doc id 15108 rev 2 3.1 clock registers the m41t66 offers 16 internal registers which contain clock, calibration, alarm, watchdog, flags, and square wave. the clock registers are memory locations which contain external (user accessible) and internal copies of the data. the external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. the internal di vider (or clock) chain will be reset upon the completion of a write to any clock address (00h to 07h). the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei ther due to a stop condition or when the pointer increments to a non-clock address. clock and alarm registers store data in bcd format. calibration, watchdog, and square wave bits are written in a binary format.
m41t66 clock operation doc id 15108 rev 2 15/34 table 2. m41t66 register map (1) 1. keys: 0 = must be set to '0' af = alarm flag (read only) afe = alarm flag enable flag bmb0 - bmb4 = watchdog multiplier bits cb0-cb1 = century bits of = oscillator fail bit ofie = oscillator fa il interrupt enable bit out = output level rb0 - rb2 = watchdog resolution bits rpt1-rpt5 = alarm repeat mode bits rs0-rs3 = sqw frequency bits s = sign bit sqwe = square wave enable bit st = stop bit wdf = watchdog flag bit (read only) addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10ths/100ths of seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h ofie 10 minutes minutes minutes 00-59 03h 0 0 10 hours hours (24 hour format) hours 00-23 04h rs3 rs2 rs1 rs0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h cb1 cb0 0 10m month century/ month 0-3/01-12 07h 10 years year year 00-99 08h out 0 s calibration calibration 09h rb2 bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah afe sqwe 0 al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 0 ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 0 0 of 0 0 flags
clock operation m41t66 16/34 doc id 15108 rev 2 3.2 calibrating the clock the m41t66 is driven by a quartz contro lled oscillator with a nom inal frequency of 32,768 hz. the accuracy of the real-time cl ock depends on the frequency of the quartz crystal that is used as the time-base for the rtc. the accuracy of the clock is dependent upon the accuracy of the crystal, and the match betwe en the capacitive load of the oscillator circuit and the capacitive load for which the cr ystal was trimmed. the m41t66 oscillator is designed for use with a 6 pf crystal load capacitance. when the calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25 c. the m41t66?s oscillator can drive the crystal?s load capaci tance that is greater than 6 pf. external capacitors must be added to achieve better clock accuracy (see figure 4 on page 7 ). the oscillation rate of crystals changes with temperature (see figure 11 on page 17 ). therefore, the m41t66 design employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circui t at the divide by 256 stage, as shown in figure 12 on page 17 . the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the calibration register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the calibration register (08h). these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 1 28 or lengthened by 2 56 oscillator cycles. if a binary '1' is loaded into the register, only th e first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 ac tual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register. assuming that the oscillator is running at exactly 32,768 hz, ea ch of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per day which corresponds to a total range of +5.5 or ?2.75 minutes per month (see figure 12 on page 17 ). two methods are available for ascertaining how much calibration the m41t66 may require: the first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934, ?how to use the digital calibration feature in timekeeper ? and serial real-time clock (rtc) products.? this allows the designer to give the end user the ability to calibrate the clock as the enviro nment requires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that accesses th e calibration byte. the second approach is better suited to a manufacturing environment, and involves the use of the sqw pin. the sqw pin will toggle at 512 hz when rs3 = '0,' rs2 = '1,' rs1 = '1,' rs0 = '0,' sqwe = ?1? and st = '0'. any deviation from 512 hz indicates the degree and direction of oscilla tor frequency shift at the test temperature. for example, a reading of 512.010124 hz would indicate a +20 ppm oscillator frequency erro r, requiring a ?10 (xx001010) to be loaded into the ca libration byte for correction. note that setting or changing th e calibration byte does not affect the square wave output frequency.
m41t66 clock operation doc id 15108 rev 2 17/34 figure 11. crystal accuracy across temperature figure 12. calibration waveform !) n &requencyppm 4emperature q # n n n n n n n n n n n nppm q # ?ppm q # + & +x4n4 / & 4 / q #? q # !)" ./2-!, 0/3)4)6% #!,)"2!4)/. .%'!4)6% #!,)"2!4)/.
clock operation m41t66 18/34 doc id 15108 rev 2 3.3 setting alarm clock registers address locations 0ah-0eh contain the alarm settings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. bits rpt5?rpt1 put the alarm in the repeat mode of operation. ta bl e 3 shows the possible configurations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5?rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set, the alarm condition activates the irq /out. to disable the alarm, write '0' to the alarm date register and to rpt5?rpt1. note: if the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to occur until the address poin ter is moved to a different address. it should also be noted that if the last address written is the ?alarm seconds,? the address pointer will incr ement to the flag address, ca using this situation to occur. the irq /out output is cleared by a read to the flags register as shown in figure 13 . a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' figure 13. alarm interrupt reset waveform table 3. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 1 1 1 1 1 once per second 1 1 1 1 0 once per minute 1 1 1 0 0 once per hour 1 1 0 0 0 once per day 1 0 0 0 0 once per month 0 0 0 0 0 once per year !,!2-&,!'")4!& &h %h h ()'( : !) )21/54
m41t66 clock operation doc id 15108 rev 2 19/34 3.4 watchdog timer the watchdog timer can be used to detect an out-of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. bits bmb4-bmb0 store a binary multiplier and the three bits rb2-rb0 select the resolution where: 000=1/16 second (16hz) 001=1/4 second (4hz) 010=1 second (1hz) 011=4 seconds (1/4hz) and 100 = 1 minute (1/60hz) note: invalid combinations (101, 110, and 111) will not enable a watchdog time-out. setting the bmb4-bmb0 = 0 with any combination of rb2- rb0, other than 000, will result in an immediate watchdog time-out. the amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (for example: writing 00001110 in the watchdog register = 3*1 or 3 seconds). if the processor does not reset the timer within the specified period, the m41t66 sets the wdf (watchdog flag) and generates an interrupt on the irq /outpin. the watchdog timer can only be reset by having the microprocessor perform a write of the watchdog register. the time-out period then starts over. should the watchdog timer time-out, any value may be written to the watchdog register in order to clear the irq /out pin. a value of 00h will disable the watchdog function until it is again programmed to a new valu e. a read of the flags regist er will reset the watchdog flag (bit d7; register 0fh). the watchdog function is automatically disabled upon power-up, and the watchdog register is cleared. note: a write to any clock register will restart the watchdog timer.
clock operation m41t66 20/34 doc id 15108 rev 2 3.5 square wave output the m41t66 offers the user a programmable square wave function which is output on the sqw pin. rs3-rs0 bits located in 04h establish the square wave output frequency. these frequencies are listed in ta bl e 4 . once the selection of the sqw frequency has been completed, the sqw pin can be turned on and off under software control with the square wave enable bit (sqwe) located in register 0ah. the sqw output is an open drain output driver. the initial power-up default for the sqw output is 32 khz. note: when the sqw is enabled and the st bit is set (st = 1), the square wave output could be low or high and could drain current through the pull-up resistor. due to the output buffer circuitry used for the sqw output, this pin must not be taken to a voltage greater than v cc . a diode is required on the sqw pin for supercap? (or battery) backup. a low threshold bat42 diode is recommended (see figure 4 on page 7 ). 3.6 century bits these two bits will increment in a binary fashio n at the turn of the century, and handle all leap years correctly. see table 6 on page 22 for additional explanation. table 4. square wave output frequency square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none? 000132.768khz 00108.192khz 00114.096khz 01002.048khz 01011.024khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
m41t66 clock operation doc id 15108 rev 2 21/34 3.7 output driver pin when the ofie bit, afe bit, and watchdog register are not set to generate an interrupt, the irq /out pin becomes an output driver that reflects the contents of d7 of the calibration register. in other words, when d7 (out bit) is a '0,' then the irq /out pin will be driven low. note: the irq /out pin is an open drain which requires an external pull-up resistor. 3.8 oscillator stop detection if the oscillator fail (of) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data. this bit will be set to '1' any time the oscillator stops. in the event the of bit is found to be set to '1' at any time other than the initial power-up, the stop bit (st) should be written to a '1,' then im mediately reset to '0.' this will restart the oscillator. the following conditions can cause the of bit to be set: the first time power is applied (defaults to a '1' on power-up). the voltage present on v cc or battery is insufficie nt to support oscillation. the st bit is set to '1.' external interference of the crystal if the oscillator fail interrupt enable bi t (ofie) is set to a '1,' the irq /outpin will also be activated. the irq /out output is cleared by resetting the ofie or of bit to '0' (not by reading the flag register). the of bit will remain set to '1' until written to logic '0.' the oscillator must start and have run for at least 1 second before attempting to reset the of bit to '0.' if the trigger event occurs during a power-down condit ion, this bit will be set correctly.
clock operation m41t66 22/34 doc id 15108 rev 2 3.9 initial power-on defaults upon application of power to the device, the regi ster bits will initially power-on in the state indicated in ta b l e 5 . table 5. initial power-on default values condition st of ofie out afe sqwe rs3-1 rs0 watchdog initial power-up (1) 1. all other control bits power-up in an undetermined state. 01 0 1 0 1 0 1 0 table 6. century bits examples cb0 cb1 leap year? example (1) 1. leap year occurs every four years (f or years evenly divisible by four), except for y ears evenly divisible by 100. the only exceptions are those years evenly divisible by 400 (the y ear 2000 was a leap year, year 2100 is not). 00yes2000 0 1 no 2100 1 0 no 2200 1 1 no 2300
m41t66 maximum ratings doc id 15108 rev 2 23/34 4 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. table 7. absolute maximum ratings sym parameter conditions (1) 1. test conforms to jedec standard. value (2) 2. data based on characterization results, not tested in production. unit t stg storage temperature (v cc off, oscillator off) ?55 to 125 c v cc supply voltage ?0.3 to 5.0 v t sld (3) 3. reflow at peak temperature of 260 c (total th ermal budget not to exceed 245 c for greater than 30 seconds). lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.2 to v cc +0.3 v i o output current 20 ma p d power dissipation 1 w v esd(hbm) electro-static discharge voltage (human body model) t a = 25 c >1500 v v esd(rcdm) electro-static discharge voltage (robotic charged device model) t a = 25 c >1000 v
dc and ac parameters m41t66 24/34 doc id 15108 rev 2 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. figure 14. ac measurement i/o waveform figure 15. crystal isolation example 1. substrate pad should be tied to v ss . 2. to avoid coupling between pin 4 (sqw) and pin 2 (xo) , pin 3 (gnd) should be routed adjacent to pin 4 for isolation purposes. table 8. operating and ac measurement conditions (1) 1. output hi-z is defined as the point where data is no longer driven. parameter m41t66 supply voltage (v cc ) 1.5 v to 4.4 v ambient operating temperature (t a ) ?40 to 85 c load capacitance (c l ) 50 pf input rise and fall times 5 ns input pulse voltages 0.2 v cc to 0.8 v cc input and output timing ref. voltages 0.3 v cc to 0.7 v cc !) 6 ## 6 ## 6 ## 6 ## !) #rystal 8) 8/ '.$ ,ocal'rounding0lane ,ayer
m41t66 dc and ac parameters doc id 15108 rev 2 25/34 table 9. capacitance symbol parameter (1)(2) min max unit c in input capacitance 7 pf c out (3) output capacitance 10 pf t lp low-pass filter input time constant (sda and scl) 50 ns 1. effective capacitance measur ed with power supply at 3.6 v; sampled only, not 100% tested. 2. at 25 c, f = 1 mhz. 3. outputs deselected. table 10. dc characteristics sym parameter test condition (1) min typ max unit v cc (2) operating voltage clock 0 c to 85 c 1.0 4.4 v ?20 c to 85 c 1.3 4.4 v ?40 c to 85 c 1.5 4.4 v i 2 c bus (400 khz) 1.3 4.4 v i cc1 supply current scl = 400 khz (no load) 4.4 v 100 a 3.6 v 50 70 a 3.0 v 35 a 2.5 v 30 a 2.0 v 20 a i cc2 supply current (standby) scl = 0 hz all inputs v cc ? 0.2 v v ss + 0.2 v sqw off 4.4 v 1100 na 3.6 v 550 900 na 3.0 v at 25 c 525 na 1.8 v at 25 c 450 na v il input low voltage ?0.2 0.3 v cc v v ih input high voltage 0.7v cc v cc +0.3 v v ol output low voltage v cc = 4.4 v, i ol = 1.0 ma (sqw, irq /out) 0.4 v v pu pull-up supply voltage (open drain) irq /out 4.4 v sqw v cc v i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a square wave duty cycle (3) no load 40 50 60 % 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 1.5 v to 4.4 v (except where noted). 2. oscillator startup guaranteed at 1.6 v only at 25 c. 3. guaranteed by design.
dc and ac parameters m41t66 26/34 doc id 15108 rev 2 table 12. oscillator characteristics figure 16. bus timing requirements sequence table 11. crystal electrical characteristics sym parameter (1)(2) 1. externally supplied if using the qfn16 package. stmicroelectroni cs recommends the citizen cfs-145 (1.5 x 5 mm) and the kds dt-38 (3 x 8 mm) for thru-hole, or the kds dmx-26s (3.2 x 8 mm) for surface-mount, tuning fork-t ype quartz crystals. kds can be contacted at http://www.kds.info/index_en.htm. citizen can be contacted at http://www. citizencrystal.com. 2. load capacitors are integrated within the m41t66. circ uit board layout considerat ions for the 32.768 khz crystal of minimum trace lengths and isolation from rf generating signal s should be taken into account. min typ max units f o resonant frequency 32.768 khz r s series resistance (t a = ?40 to 70 c) 75 (3)(4) 3. guaranteed by design. 4. r s (max) = 65 k for t a = ?40 to 85 c and oscillator startup at 1.7 v. k c l load capacitance 6 pf 7-12.5 (5) 5. external capactors must be added to achieve better clock accuracy. symbol parameter conditions min typ max unit v sta oscillator start voltage at 25 c 1.6 v t sta oscillator start time v cc = 1.6 v at 25 c 500 ms v cc = 3.0 v 1 s c g xin 12 pf c d xout 12 pf ic-to-ic frequency variation (1) 1. reference value. t a = 25 c, v cc = 3.0 v, cmj-145 (c l = 6 pf, 32,768 hz) manufactured by citizen. ?10 +10 ppm !) 3$! 0 t353 4/ t3534! t($3 4! 32 3#, t35$!4 t& t($$!4 t2 t()'( t,/7 t($34! t"5& 3 0
m41t66 dc and ac parameters doc id 15108 rev 2 27/34 table 13. ac characteristics sym parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 1.5 to 4.4 v (except where noted). min typ max units f scl scl clock frequency 0 400 khz t low clock low period 1.3 s t high clock high period 600 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:dat (2) 2. transmitter must internally provi de a hold time to bridge the undefined re gion (300 ns max) of the falling edge of scl. data setup time 100 ns t hd:dat data hold time 0 s t su:sto stop condition setup time 600 ns t buf time the bus must be free before a new transmission can start 1.3 s
package mechanical data m41t66 28/34 doc id 15108 rev 2 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 17. qfn16 ? 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline 1. drawing is not to scale. ! ! ! e + + b #h $ % , % $ ddd 1&. ! #
m41t66 package mechanical data doc id 15108 rev 2 29/34 table 14. qfn16 ? 16-lead, quad, flat package, no lead, 3 x 3 mm body size, mech. data figure 18. qfn16 ? 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended footprint 1. dimensions shown are in millimeters (mm). figure 19. 32 khz crystal + qfn16 vs. vsoj20 mechanical data 1. dimensions shown are in millimeters (mm). symb mm inches typ min max typ min max a 0.90 0.80 1.00 0.035 0.032 0.039 a1 0.02 0.00 0.05 0.001 0.000 0.002 a3 0.20 ? ? 0.008 ? ? b 0.25 0.18 0.30 0.010 0.007 0.012 d 3.00 2.90 3.10 0.118 0.114 0.122 d2 1.70 1.55 1.80 0.067 0.061 0.071 e 3.00 2.90 3.10 0.118 0.114 0.122 e2 1.70 1.55 1.80 0.067 0.061 0.071 e0.50? ?0.020? ? k0.20? ?0.008? ? l 0.40 0.30 0.50 0.016 0.012 0.020 ddd ? 0.08 ? ? 0.003 ? ch ? 0.33 ? ? 0.013 ? n16 16 !) 8) 8/ !) 341&. 3-4 #2934!, 63/* ? ?
package mechanical data m41t66 30/34 doc id 15108 rev 2 figure 20. carrier tape for qfn16 (3 mm x 3 mm) package t k 0 p 1 a 0 b 0 p 2 p 0 center line s of cavity w e f d top cover tape u s er direction of feed am0 3 07 3 v1 table 15. carrier tape dimensions for qfn16 (3 mm x 3 mm) package package w d e p 0 p 2 fa 0 b 0 k 0 p 1 tunit bulk qty qfn16 12.00 0.30 1.50 + 0.10 /-0.00 1.75 0.10 4.00 0.10 2.00 0.10 5.50 0.05 3.30 0.10 3.30 0.10 1.10 0.10 8.00 0.10 0.30 0.05 mm 3000
m41t66 package mechanical data doc id 15108 rev 2 31/34 figure 21. reel schematic note: the dimensions given in ta b l e 1 6 incorporate tolerances that cover all variations on critical parameters. a d b f u ll r a di us t a pe s lot in core for t a pe s t a rt 2.5mm min.width g me asu red at h ub c n 40mm min. acce ss hole at s lot loc a tion t am0492 8 v1 table 16. reel dimensions for 12 mm carrier tape - qfn16 package a (max) b (min) c d (min) n (min) g t (max) 330 mm (13-inch) 1.5 mm 13 mm 0.2 mm 20.2 mm 60 mm 12.4 mm + 2/?0 mm 18.4 mm
part numbering m41t66 32/34 doc id 15108 rev 2 7 part numbering table 17. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m41t 66 q 6 f device family m41t device type and supply voltage 66 = v cc = 1.5 v to 4.4 v package q = qfn16 (3 mm x 3 mm) temperature range 6 = ?40 c to 85 c shipping method f = ecopack ? package, tape & reel
m41t66 revision history doc id 15108 rev 2 33/34 8 revision history table 18. document revision history date revision changes 22-oct-2008 1 initial release 25-oct-2011 2 updated title; minor textual updates; updated ecopack ? text in section 6: package mechanical data ; added figure 20 , 21 , ta b l e 1 5 , 16
m41t66 34/34 doc id 15108 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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